Silicon Labs /EFR32FG23B020F512IM40 /SYSRTC0_NS /GRP0_CTRL

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Interpret as GRP0_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMP0EN)CMP0EN 0 (CMP1EN)CMP1EN 0 (CAP0EN)CAP0EN 0 (CLEAR)CMP0CMOA 0 (CLEAR)CMP1CMOA 0 (RISING)CAP0EDGE

CAP0EDGE=RISING, CMP1CMOA=CLEAR, CMP0CMOA=CLEAR

Description

No Description

Fields

CMP0EN

Compare 0 Enable

CMP1EN

Compare 1 Enable

CAP0EN

Capture 0 Enable

CMP0CMOA

Compare 0 Compare Match Output Action

0 (CLEAR): Cleared on the next cycle

1 (SET): Set on the next cycle

2 (PULSE): Set on the next cycle, cleared on the cycle after

3 (TOGGLE): Inverted on the next cycle

4 (CMPIF): Export this channel’s CMP IF

CMP1CMOA

Compare 1 Compare Match Output Action

0 (CLEAR): Cleared on the next cycle

1 (SET): Set on the next cycle

2 (PULSE): Set on the next cycle, cleared on the cycle after

3 (TOGGLE): Inverted on the next cycle

4 (CMPIF): Export this channel’s CMP IF

CAP0EDGE

Capture 0 Edge Select

0 (RISING): Rising edges detected

1 (FALLING): Falling edges detected

2 (BOTH): Both edges detected

Links

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